1. Field of the Invention
The present invention relates to test sockets for vertical surface mount packaged semiconductor devices. In particular, the present invention relates to test sockets for vertical surface mount packaged semiconductor devices which include bent leads. More particularly, the test socket of the present invention engages and readily releases the leads of one or more vertical surface mount packages.
2. Background of Related Art
Semiconductor devices are routinely subjected to testing for compliance with certain electrical performance requirements and burn-in testing. Numerous test sockets have been developed for these purposes. Many such test sockets have been designed for use with a particular type of packaged semiconductor devices, such as dual in-line packages (DIPs), small outline packages (SOPs), small outline J-leaded packages (SOJs), and quad flat packages (QFPs).
Many test sockets include several electrically conductive terminals for establishing an electrical connection between one or more packaged semiconductor devices and a testing device attached to the test socket. Typically, such test sockets include several small, movable parts. Exemplary devices are found in the following U.S. Pat. Nos. 3,573,617 (the "'617 patent"), issued to Ellwood A. Randolph, et al. on Apr. 6, 1971; 4,461,525 (the "'525 patent"), issued to Wendell L. Griffin on Jul. 24, 1984; 5,020,998 (the "'998 patent"), issued to Kiyokazu Ikeya and Masanori Yagi on Jun. 4, 1991; 5,208,529 (the "'529 patent"), issued to Kazuyuki Tsurishima and Teruaki Sakurada on May 4, 1993; 5,489,854 (the "'854 patent"), issued to Roy V. Buck and David N. Tesh on Feb. 6, 1996; 5,609,489 (the "'489 patent"), issued to Joel D. Bickford and Julius K. Botka on Mar. 11, 1997; and 5,628,635 (the "'635 patent"), issued to Kiyokazu Ikeya on May 13, 1997.
However, such test sockets are typically compatible with only a single type of packaged semiconductor device. Moreover, the parts of many test sockets in the prior art tend to wear under repeated use. Many test sockets are also problematic from the standpoint that the contacts thereof fail to accurately approximate the electrical connections that connect a packaged semiconductor device with a carrier substrate in actual use.
Many test sockets employ a cover or other device to ensure adequate electrical contact between the tested packaged semiconductor device and the test socket. The '998, '529, '854 and '489 patents each disclose test sockets which require the use of a cover or similar contact-ensuring device.
However, such devices typically exert force on the packaged semiconductor device, which could bend or otherwise damage the typically delicate leads that extend therefrom, as well as other parts of the packaged semiconductor device. Thus, the use of covers and other devices to force a packaged semiconductor device onto a test socket is somewhat undesirable. Moreover, covers and other contact-ensuring devices tend to prevent adequate heat transfer away from the tested package, and may therefore fail to recreate the conditions to which the packaged semiconductor device will be subjected in use. Further, covers and other such devices tend to be complex, increasing the cost of test sockets and the amount of time that is required to test packaged semiconductor devices.
Other test sockets clamp onto or otherwise apply force to a small portion of the leads of the tested packaged semiconductor device to establish an interference fit-type electrical contact between the leads and their corresponding terminals of the test socket. Exemplary devices are disclosed in the '617, '525 and '529 patents.
However, the use of clamps or other devices that unevenly exert force on the leads may bend or otherwise damage the typically delicate leads. Moreover, due to wear from repeated use, some test sockets fail to approximate the ohmic contact that would be made in actual use of the packaged semiconductor device. Thus, such test sockets may contribute to the generation of inaccurate test results.
What is needed is a test socket for vertical surface mount packaged semiconductor devices which approximates the actual use conditions to which the semiconductor device will be subjected, which facilitates the testing of several packaged semiconductor devices and is capable of frequently repeating the testing process on new sets of packaged semiconductor devices, and which protects and maintains the shape of the leads.